\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/stm32h7xx\+\_\+hal\+\_\+spi.h File Reference}
\hypertarget{stm32h7xx__hal__spi_8h}{}\label{stm32h7xx__hal__spi_8h}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_spi.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_spi.h}}


Header file of SPI HAL module.  


{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+def.\+h"{}}\newline
{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+spi\+\_\+ex.\+h"{}}\newline
\doxysubsubsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_s_p_i___init_type_def}{SPI\+\_\+\+Init\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em SPI Configuration Structure definition. \end{DoxyCompactList}\item 
struct \mbox{\hyperlink{struct_____s_p_i___handle_type_def}{\+\_\+\+\_\+\+SPI\+\_\+\+Handle\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em SPI handle Structure definition. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define {\bfseries SPI\+\_\+\+LOWEND\+\_\+\+FIFO\+\_\+\+SIZE}~8UL
\item 
\#define {\bfseries SPI\+\_\+\+HIGHEND\+\_\+\+FIFO\+\_\+\+SIZE}~16UL
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_gaac0006cdf5670741f8702e55d4bf4601}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+NONE}}~(0x00000000\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_ga75f5edd4e2a7a95bc9a994244df52460}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+MODF}}~(0x00000001\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_gad1163823ec5fa89e4670366565d4ab93}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+CRC}}~(0x00000002\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_ga9587f998fed196a4f30c38f2da731c0f}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+OVR}}~(0x00000004\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_gaf03238e57dd0c4d277fef2aa7a083133}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+FRE}}~(0x00000008\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_gaaf91992131301e3fc7f2ce62fb011f6c}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+DMA}}~(0x00000010\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_ga777b36b52caf926a384976baf34530a3}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+FLAG}}~(0x00000020\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_gab7fa15838d5ef9316ed8a0ec1c782fb7}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+ABORT}}~(0x00000040\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_ga58d86c21484e1d1fe3027ec2771706cc}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+UDR}}~(0x00000080\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_ga67dd5b4fb30d2e506e5900261eec47ba}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+TIMEOUT}}~(0x00000100\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_ga81d13d9d60c821fea6f2e993e656f92a}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+UNKNOW}}~(0x00000200\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_ga4e6d9b12a40b3c6ac209f0e711ba3397}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+NOT\+\_\+\+SUPPORTED}}~(0x00000400\+UL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___error___code_gacc0d4d1cc59ba95a075fd6244505d4ed}{HAL\+\_\+\+SPI\+\_\+\+ERROR\+\_\+\+RELOAD}}~(0x00000800\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MODE\+\_\+\+SLAVE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MODE\+\_\+\+MASTER}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae374f7d95b2b790e5741a84932b8c63f}{SPI\+\_\+\+CFG2\+\_\+\+MASTER}}
\item 
\#define {\bfseries SPI\+\_\+\+DIRECTION\+\_\+2\+LINES}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DIRECTION\+\_\+2\+LINES\+\_\+\+TXONLY}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab19c27afabbaf50a9e02e2aa0f489383}{SPI\+\_\+\+CFG2\+\_\+\+COMM\+\_\+0}}
\item 
\#define {\bfseries SPI\+\_\+\+DIRECTION\+\_\+2\+LINES\+\_\+\+RXONLY}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8577b6cfe88294c5f4326d795338b252}{SPI\+\_\+\+CFG2\+\_\+\+COMM\+\_\+1}}
\item 
\#define {\bfseries SPI\+\_\+\+DIRECTION\+\_\+1\+LINE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1b7bf18425d7ade65a2e772fde619bf1}{SPI\+\_\+\+CFG2\+\_\+\+COMM}}
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+4\+BIT}~(0x00000003\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+5\+BIT}~(0x00000004\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+6\+BIT}~(0x00000005\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+7\+BIT}~(0x00000006\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+8\+BIT}~(0x00000007\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+9\+BIT}~(0x00000008\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+10\+BIT}~(0x00000009\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+11\+BIT}~(0x0000000\+AUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+12\+BIT}~(0x0000000\+BUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+13\+BIT}~(0x0000000\+CUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+14\+BIT}~(0x0000000\+DUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+15\+BIT}~(0x0000000\+EUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+16\+BIT}~(0x0000000\+FUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+17\+BIT}~(0x00000010\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+18\+BIT}~(0x00000011\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+19\+BIT}~(0x00000012\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+20\+BIT}~(0x00000013\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+21\+BIT}~(0x00000014\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+22\+BIT}~(0x00000015\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+23\+BIT}~(0x00000016\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+24\+BIT}~(0x00000017\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+25\+BIT}~(0x00000018\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+26\+BIT}~(0x00000019\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+27\+BIT}~(0x0000001\+AUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+28\+BIT}~(0x0000001\+BUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+29\+BIT}~(0x0000001\+CUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+30\+BIT}~(0x0000001\+DUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+31\+BIT}~(0x0000001\+EUL)
\item 
\#define {\bfseries SPI\+\_\+\+DATASIZE\+\_\+32\+BIT}~(0x0000001\+FUL)
\item 
\#define {\bfseries SPI\+\_\+\+POLARITY\+\_\+\+LOW}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+POLARITY\+\_\+\+HIGH}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf9e5874b94f69e2af8d7fd460ff33460}{SPI\+\_\+\+CFG2\+\_\+\+CPOL}}
\item 
\#define {\bfseries SPI\+\_\+\+PHASE\+\_\+1\+EDGE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+PHASE\+\_\+2\+EDGE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga268bfe1b80b116394eef88b75cd3bcbd}{SPI\+\_\+\+CFG2\+\_\+\+CPHA}}
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+SOFT}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad0e7364142f9a7eb6b5c59897dd8b72d}{SPI\+\_\+\+CFG2\+\_\+\+SSM}}
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+HARD\+\_\+\+INPUT}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+HARD\+\_\+\+OUTPUT}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9c9863c4e8e013e090efbe2cc7d82c45}{SPI\+\_\+\+CFG2\+\_\+\+SSOE}}
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+PULSE\+\_\+\+DISABLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+PULSE\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gabe0131b6501f637fa0168c031050818d}{SPI\+\_\+\+CFG2\+\_\+\+SSOM}}
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+2}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+4}~(0x10000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+8}~(0x20000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+16}~(0x30000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+32}~(0x40000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+64}~(0x50000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+128}~(0x60000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+BAUDRATEPRESCALER\+\_\+256}~(0x70000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIRSTBIT\+\_\+\+MSB}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIRSTBIT\+\_\+\+LSB}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaff6b7fae6de0289fd47beb27c3120b9}{SPI\+\_\+\+CFG2\+\_\+\+LSBFRST}}
\item 
\#define {\bfseries SPI\+\_\+\+TIMODE\+\_\+\+DISABLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+TIMODE\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2a319d6039b6cc10375d0100979616b}{SPI\+\_\+\+CFG2\+\_\+\+SP\+\_\+0}}
\item 
\#define {\bfseries SPI\+\_\+\+CRCCALCULATION\+\_\+\+DISABLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRCCALCULATION\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25e56eef69334cb723e24a8d33fb0ef5}{SPI\+\_\+\+CFG1\+\_\+\+CRCEN}}
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+\+DATASIZE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+4\+BIT}~(0x00030000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+5\+BIT}~(0x00040000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+6\+BIT}~(0x00050000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+7\+BIT}~(0x00060000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+8\+BIT}~(0x00070000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+9\+BIT}~(0x00080000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+10\+BIT}~(0x00090000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+11\+BIT}~(0x000\+A0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+12\+BIT}~(0x000\+B0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+13\+BIT}~(0x000\+C0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+14\+BIT}~(0x000\+D0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+15\+BIT}~(0x000\+E0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+16\+BIT}~(0x000\+F0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+17\+BIT}~(0x00100000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+18\+BIT}~(0x00110000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+19\+BIT}~(0x00120000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+20\+BIT}~(0x00130000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+21\+BIT}~(0x00140000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+22\+BIT}~(0x00150000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+23\+BIT}~(0x00160000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+24\+BIT}~(0x00170000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+25\+BIT}~(0x00180000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+26\+BIT}~(0x00190000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+27\+BIT}~(0x001\+A0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+28\+BIT}~(0x001\+B0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+29\+BIT}~(0x001\+C0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+30\+BIT}~(0x001\+D0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+31\+BIT}~(0x001\+E0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+LENGTH\+\_\+32\+BIT}~(0x001\+F0000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+01\+DATA}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+02\+DATA}~(0x00000020\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+03\+DATA}~(0x00000040\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+04\+DATA}~(0x00000060\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+05\+DATA}~(0x00000080\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+06\+DATA}~(0x000000\+A0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+07\+DATA}~(0x000000\+C0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+08\+DATA}~(0x000000\+E0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+09\+DATA}~(0x00000100\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+10\+DATA}~(0x00000120\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+11\+DATA}~(0x00000140\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+12\+DATA}~(0x00000160\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+13\+DATA}~(0x00000180\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+14\+DATA}~(0x000001\+A0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+15\+DATA}~(0x000001\+C0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+FIFO\+\_\+\+THRESHOLD\+\_\+16\+DATA}~(0x000001\+E0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+INITIALIZATION\+\_\+\+ALL\+\_\+\+ZERO\+\_\+\+PATTERN}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+CRC\+\_\+\+INITIALIZATION\+\_\+\+ALL\+\_\+\+ONE\+\_\+\+PATTERN}~(0x00000001\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+POLARITY\+\_\+\+LOW}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+NSS\+\_\+\+POLARITY\+\_\+\+HIGH}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa1829b079924734042d20b1671fecc1d}{SPI\+\_\+\+CFG2\+\_\+\+SSIOP}}
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+KEEP\+\_\+\+IO\+\_\+\+STATE\+\_\+\+DISABLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+KEEP\+\_\+\+IO\+\_\+\+STATE\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0d90225cbbced8ab5c382605500e6b8}{SPI\+\_\+\+CFG2\+\_\+\+AFCNTR}}
\item 
\#define {\bfseries SPI\+\_\+\+IO\+\_\+\+SWAP\+\_\+\+DISABLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+IO\+\_\+\+SWAP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6a392a021319a1e0fdf422502cfa47f2}{SPI\+\_\+\+CFG2\+\_\+\+IOSWP}}
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+00\+CYCLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+01\+CYCLE}~(0x00000001\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+02\+CYCLE}~(0x00000002\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+03\+CYCLE}~(0x00000003\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+04\+CYCLE}~(0x00000004\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+05\+CYCLE}~(0x00000005\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+06\+CYCLE}~(0x00000006\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+07\+CYCLE}~(0x00000007\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+08\+CYCLE}~(0x00000008\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+09\+CYCLE}~(0x00000009\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+10\+CYCLE}~(0x0000000\+AUL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+11\+CYCLE}~(0x0000000\+BUL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+12\+CYCLE}~(0x0000000\+CUL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+13\+CYCLE}~(0x0000000\+DUL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+14\+CYCLE}~(0x0000000\+EUL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+SS\+\_\+\+IDLENESS\+\_\+15\+CYCLE}~(0x0000000\+FUL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+00\+CYCLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+01\+CYCLE}~(0x00000010\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+02\+CYCLE}~(0x00000020\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+03\+CYCLE}~(0x00000030\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+04\+CYCLE}~(0x00000040\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+05\+CYCLE}~(0x00000050\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+06\+CYCLE}~(0x00000060\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+07\+CYCLE}~(0x00000070\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+08\+CYCLE}~(0x00000080\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+09\+CYCLE}~(0x00000090\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+10\+CYCLE}~(0x000000\+A0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+11\+CYCLE}~(0x000000\+B0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+12\+CYCLE}~(0x000000\+C0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+13\+CYCLE}~(0x000000\+D0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+14\+CYCLE}~(0x000000\+E0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+INTERDATA\+\_\+\+IDLENESS\+\_\+15\+CYCLE}~(0x000000\+F0\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+RX\+\_\+\+AUTOSUSP\+\_\+\+DISABLE}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+MASTER\+\_\+\+RX\+\_\+\+AUTOSUSP\+\_\+\+ENABLE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae7d399759fc0606d8ef44845004a9faf}{SPI\+\_\+\+CR1\+\_\+\+MASRX}}
\item 
\#define {\bfseries SPI\+\_\+\+UNDERRUN\+\_\+\+BEHAV\+\_\+\+REGISTER\+\_\+\+PATTERN}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+UNDERRUN\+\_\+\+BEHAV\+\_\+\+LAST\+\_\+\+RECEIVED}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa77dbb8777fc83d62910a7775b26870b}{SPI\+\_\+\+CFG1\+\_\+\+UDRCFG\+\_\+0}}
\item 
\#define {\bfseries SPI\+\_\+\+UNDERRUN\+\_\+\+BEHAV\+\_\+\+LAST\+\_\+\+TRANSMITTED}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2ef84d2d59adad7d35f91769218fcd5}{SPI\+\_\+\+CFG1\+\_\+\+UDRCFG\+\_\+1}}
\item 
\#define {\bfseries SPI\+\_\+\+UNDERRUN\+\_\+\+DETECT\+\_\+\+BEGIN\+\_\+\+DATA\+\_\+\+FRAME}~(0x00000000\+UL)
\item 
\#define {\bfseries SPI\+\_\+\+UNDERRUN\+\_\+\+DETECT\+\_\+\+END\+\_\+\+DATA\+\_\+\+FRAME}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7fbc8512d964f194d96bba1e5dd7582f}{SPI\+\_\+\+CFG1\+\_\+\+UDRDET\+\_\+0}}
\item 
\#define {\bfseries SPI\+\_\+\+UNDERRUN\+\_\+\+DETECT\+\_\+\+BEGIN\+\_\+\+ACTIVE\+\_\+\+NSS}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaced6f95340b0146aa0f172f766f1b92c}{SPI\+\_\+\+CFG1\+\_\+\+UDRDET\+\_\+1}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+RXP}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga87b292843107573ae82aa13d88916646}{SPI\+\_\+\+IER\+\_\+\+RXPIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+TXP}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga40ad06dce5bd7f4f2d1db25e8ecd33a4}{SPI\+\_\+\+IER\+\_\+\+TXPIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+DXP}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5fde811db0bae41847c2c56d20e1983b}{SPI\+\_\+\+IER\+\_\+\+DXPIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+EOT}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd814e85e0f2cc9fd5fbedbd1db232c1}{SPI\+\_\+\+IER\+\_\+\+EOTIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+TXTF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf329c2e8fb5112c4efdcac4c69bf95fb}{SPI\+\_\+\+IER\+\_\+\+TXTFIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+UDR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga33d0436c4b553cc357b52b9ecaaf542f}{SPI\+\_\+\+IER\+\_\+\+UDRIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+OVR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ba53086c19a3260e0555ace5d700c42}{SPI\+\_\+\+IER\+\_\+\+OVRIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+CRCERR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga298b617fdd0e3d18562509839aa72fa3}{SPI\+\_\+\+IER\+\_\+\+CRCEIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+FRE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga07f63f1611444f70daf6b08fc18490ee}{SPI\+\_\+\+IER\+\_\+\+TIFREIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+MODF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d05af6bd42d7191edec2763928dee98}{SPI\+\_\+\+IER\+\_\+\+MODFIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+TSERF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1a4844bc9d90e49ba0dcacf7787f2e16}{SPI\+\_\+\+IER\+\_\+\+TSERFIE}}
\item 
\#define {\bfseries SPI\+\_\+\+IT\+\_\+\+ERR}~(SPI\+\_\+\+IT\+\_\+\+UDR \texorpdfstring{$\vert$}{|} SPI\+\_\+\+IT\+\_\+\+OVR \texorpdfstring{$\vert$}{|} SPI\+\_\+\+IT\+\_\+\+FRE \texorpdfstring{$\vert$}{|} SPI\+\_\+\+IT\+\_\+\+MODF \texorpdfstring{$\vert$}{|} SPI\+\_\+\+IT\+\_\+\+CRCERR)
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+RXP}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95289b0733d92829f9f0189574dc1d54}{SPI\+\_\+\+SR\+\_\+\+RXP}}     /\texorpdfstring{$\ast$}{*} SPI status flag \+: Rx-\/Packet available flag                 \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+TXP}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9f7199bbdd797f0238aaaf9cc42e4f64}{SPI\+\_\+\+SR\+\_\+\+TXP}}     /\texorpdfstring{$\ast$}{*} SPI status flag \+: Tx-\/Packet space available flag           \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+DXP}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga73f785111c63d6e951018ebc0fffacf6}{SPI\+\_\+\+SR\+\_\+\+DXP}}     /\texorpdfstring{$\ast$}{*} SPI status flag \+: Duplex Packet flag                       \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+EOT}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadf6af11782cace2048e20c18d4d63e1a}{SPI\+\_\+\+SR\+\_\+\+EOT}}     /\texorpdfstring{$\ast$}{*} SPI status flag \+: End of transfer flag                     \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+TXTF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac0e93a296bc722bab78d526bf1cc2f7d}{SPI\+\_\+\+SR\+\_\+\+TXTF}}    /\texorpdfstring{$\ast$}{*} SPI status flag \+: Transmission Transfer Filled flag        \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+UDR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13d3292e963499c0e9a36869909229e6}{SPI\+\_\+\+SR\+\_\+\+UDR}}     /\texorpdfstring{$\ast$}{*} SPI Error flag  \+: Underrun flag                            \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+OVR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa8d902302c5eb81ce4a57029de281232}{SPI\+\_\+\+SR\+\_\+\+OVR}}     /\texorpdfstring{$\ast$}{*} SPI Error flag  \+: Overrun flag                             \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+CRCERR}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4c0cf2db0d5d372242e66e6d7da50b39}{SPI\+\_\+\+SR\+\_\+\+CRCE}}    /\texorpdfstring{$\ast$}{*} SPI Error flag  \+: CRC error flag                           \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+FRE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf3e3c940fb46d8b32456c59819e615be}{SPI\+\_\+\+SR\+\_\+\+TIFRE}}   /\texorpdfstring{$\ast$}{*} SPI Error flag  \+: TI mode frame format error flag          \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+MODF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gabaa043349833dc7b8138969c64f63adf}{SPI\+\_\+\+SR\+\_\+\+MODF}}    /\texorpdfstring{$\ast$}{*} SPI Error flag  \+: Mode fault flag                          \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+TSERF}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5332b248a3daf660df7f13098e75da46}{SPI\+\_\+\+SR\+\_\+\+TSERF}}   /\texorpdfstring{$\ast$}{*} SPI status flag \+: Additional number of data reloaded flag  \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+SUSP}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3294b6597873bd2c0f2acb9e722e18cc}{SPI\+\_\+\+SR\+\_\+\+SUSP}}    /\texorpdfstring{$\ast$}{*} SPI status flag \+: Transfer suspend complete flag           \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+TXC}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1695e2f6e8d042aeae4d9f07e96dfe1a}{SPI\+\_\+\+SR\+\_\+\+TXC}}     /\texorpdfstring{$\ast$}{*} SPI status flag \+: Tx\+FIFO transmission complete flag        \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+FRLVL}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga09c4e3cd9a199757d6f3ac06e5bc110f}{SPI\+\_\+\+SR\+\_\+\+RXPLVL}}  /\texorpdfstring{$\ast$}{*} SPI status flag \+: Fifo reception level flag                \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+FLAG\+\_\+\+RXWNE}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab6334377efffc8f2733962c827a4bf03}{SPI\+\_\+\+SR\+\_\+\+RXWNE}}   /\texorpdfstring{$\ast$}{*} SPI status flag \+: Rx\+FIFO word not empty flag               \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+RX\+\_\+\+FIFO\+\_\+0\+PACKET}~(0x00000000\+UL)         /\texorpdfstring{$\ast$}{*} 0 or multiple of 4 packets available in the Rx\+FIFO \texorpdfstring{$\ast$}{*}/
\item 
\#define {\bfseries SPI\+\_\+\+RX\+\_\+\+FIFO\+\_\+1\+PACKET}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga927d85d0857d7a63232e1668f30957b2}{SPI\+\_\+\+SR\+\_\+\+RXPLVL\+\_\+0}})
\item 
\#define {\bfseries SPI\+\_\+\+RX\+\_\+\+FIFO\+\_\+2\+PACKET}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga06d2c44cda484d3ac4dc9d81cf056183}{SPI\+\_\+\+SR\+\_\+\+RXPLVL\+\_\+1}})
\item 
\#define {\bfseries SPI\+\_\+\+RX\+\_\+\+FIFO\+\_\+3\+PACKET}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga06d2c44cda484d3ac4dc9d81cf056183}{SPI\+\_\+\+SR\+\_\+\+RXPLVL\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga927d85d0857d7a63232e1668f30957b2}{SPI\+\_\+\+SR\+\_\+\+RXPLVL\+\_\+0}})
\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga0d846f9517715960873e854b4a0790b0}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+RESET\+\_\+\+HANDLE\+\_\+\+STATE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Reset SPI handle state. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga76064652f6f56d8868720b5541e854f5}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+ENABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enable the specified SPI interrupts. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga47fa7321c5755bfbff1a7229fbe5b21c}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+DISABLE\+\_\+\+IT}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Disable the specified SPI interrupts. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_gabdaab061e4603331a0ec4b9d651df0b5}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+GET\+\_\+\+IT\+\_\+\+SOURCE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+INTERRUPT\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check whether the specified SPI interrupt source is enabled or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_gaa0bbe5fb55f93fd277ddb6acf58cec53}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+GET\+\_\+\+FLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+FLAG\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Check whether the specified SPI flag is set or not. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_gad1cb4100b67726531ad426d300f4cd26}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+CRCERRFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI CRCERR pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga6c88becbe528c542156bc201622efba2}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+MODFFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI MODF pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_gaf6af33b1c5d334b9fe7bb778c5b6442e}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+OVRFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI OVR pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga7ff182f5cf6c731318c882351d6d7ac2}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+FREFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI FRE pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga788e7e6782849d79499064b05050627e}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+UDRFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI UDR pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga82b82dd74c0fe69c823e92323fde890a}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+EOTFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI EOT pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_gac4e14a47b0110348bb2edf1eb6023a50}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+TXTFFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI UDR pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga76cb5dc888df5c6d19675e4d076b750d}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+SUSPFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI SUSP pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga9a45859eee2e15a4a6367cc4a5066c8b}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+CLEAR\+\_\+\+TSERFFLAG}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Clear the SPI TSERF pending flag. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_ga16d2d73c2b16004499ae8d492e71fd4e}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+ENABLE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Enable the SPI peripheral. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___exported___macros_gaa10d88f87d16de53bd81dfb33bd56959}{\+\_\+\+\_\+\+HAL\+\_\+\+SPI\+\_\+\+DISABLE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Disable the SPI peripheral. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gae3b2eb5e818e58b66474d42dedac5523}{SPI\+\_\+1\+LINE\+\_\+\+TX}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Set the SPI transmit-\/only mode in 1Line configuration. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gaa8d58cef91c1874d5a4dde4014cf6269}{SPI\+\_\+1\+LINE\+\_\+\+RX}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Set the SPI receive-\/only mode in 1Line configuration. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga2e139e6f86af7b6f2690e679b0303162}{SPI\+\_\+2\+LINES\+\_\+\+TX}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Set the SPI transmit-\/only mode in 2Lines configuration. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga39089f4a0d840c0748936a574142c8fa}{SPI\+\_\+2\+LINES\+\_\+\+RX}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Set the SPI receive-\/only mode in 2Lines configuration. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga5ff90af4675f015852b14e755ce79e08}{SPI\+\_\+2\+LINES}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Set the SPI Transmit-\/\+Receive mode in 2Lines configuration. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gad5135300763c75dbb446861536359f12}{IS\+\_\+\+SPI\+\_\+\+MODE}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga8ce4827db741ff965ea0cb1c105b00d5}{IS\+\_\+\+SPI\+\_\+\+DIRECTION}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga79454622381b22d02c8cdd3346c80f78}{IS\+\_\+\+SPI\+\_\+\+DIRECTION\+\_\+2\+LINES}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga28006c88236f1a94f4e69d9d868f21fe}{IS\+\_\+\+SPI\+\_\+\+DIRECTION\+\_\+2\+LINES\+\_\+\+OR\+\_\+1\+LINE\+\_\+2\+LINES\+\_\+\+TXONLY}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gad0d8a45ecf7ef088463d1b818bd09826}{IS\+\_\+\+SPI\+\_\+\+DIRECTION\+\_\+2\+LINES\+\_\+\+OR\+\_\+1\+LINE\+\_\+2\+LINES\+\_\+\+RXONLY}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gab6f9f528f7eb70373b9caf3548e44e67}{IS\+\_\+\+SPI\+\_\+\+DATASIZE}}(DATASIZE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga3f1e514b528933ad992018edcf97e23b}{IS\+\_\+\+SPI\+\_\+\+FIFOTHRESHOLD}}(THRESHOLD)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gafc1cc5b1ff7e801a409a7a1e6047acf9}{IS\+\_\+\+SPI\+\_\+\+CPOL}}(CPOL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga6441f08edf79dd5b243c54b888d3cbf7}{IS\+\_\+\+SPI\+\_\+\+CPHA}}(CPHA)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gabbeedf42eccef1bae4f88c606fc3b261}{IS\+\_\+\+SPI\+\_\+\+NSS}}(NSS)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga9bbb9935c81663db6b96a2cb08ef6006}{IS\+\_\+\+SPI\+\_\+\+NSSP}}(NSSP)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gae79f46ed9f91e39dc1f6912cb25fc716}{IS\+\_\+\+SPI\+\_\+\+BAUDRATE\+\_\+\+PRESCALER}}(PRESCALER)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gabee8e0302741f4a5c41b96af640c63ad}{IS\+\_\+\+SPI\+\_\+\+FIRST\+\_\+\+BIT}}(BIT)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga812f7bf5919bc6e45727d6ac05c60b49}{IS\+\_\+\+SPI\+\_\+\+TIMODE}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga96e66460d09a553fd9996c53dcc4b252}{IS\+\_\+\+SPI\+\_\+\+CRC\+\_\+\+CALCULATION}}(CALCULATION)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gad39542cb3b654effe9c4e3d8079884ba}{IS\+\_\+\+SPI\+\_\+\+CRC\+\_\+\+INITIALIZATION\+\_\+\+PATTERN}}(PATTERN)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga393003a5b035758f07c7243738c5f463}{IS\+\_\+\+SPI\+\_\+\+CRC\+\_\+\+LENGTH}}(LENGTH)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga76eec5bbb44c873aa52966a9cb6c8f8c}{IS\+\_\+\+SPI\+\_\+\+CRC\+\_\+\+POLYNOMIAL}}(POLYNOMIAL)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga9bc863efd4059e29b055978c9eb36909}{IS\+\_\+\+SPI\+\_\+\+CRC\+\_\+\+POLYNOMIAL\+\_\+\+SIZE}}(POLYNOM,  LENGTH)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga17f299bb0d8e36dbeb43457a7c521328}{IS\+\_\+\+SPI\+\_\+\+UNDERRUN\+\_\+\+DETECTION}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_gaa3d1fe42e2147532ac110d26904ebd32}{IS\+\_\+\+SPI\+\_\+\+UNDERRUN\+\_\+\+BEHAVIOUR}}(MODE)
\item 
\#define \mbox{\hyperlink{group___s_p_i___private___macros_ga5810568855b1df12700af47c4c4fad61}{IS\+\_\+\+SPI\+\_\+\+MASTER\+\_\+\+RX\+\_\+\+AUTOSUSP}}(MODE)
\end{DoxyCompactItemize}
\doxysubsubsection*{Typedefs}
\begin{DoxyCompactItemize}
\item 
typedef struct \mbox{\hyperlink{struct_____s_p_i___handle_type_def}{\+\_\+\+\_\+\+SPI\+\_\+\+Handle\+Type\+Def}} {\bfseries SPI\+\_\+\+Handle\+Type\+Def}
\begin{DoxyCompactList}\small\item\em SPI handle Structure definition. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Enumerations}
\begin{DoxyCompactItemize}
\item 
enum \mbox{\hyperlink{group___s_p_i___exported___types_ga8891cb64e76198a860172d94c638c9b4}{HAL\+\_\+\+SPI\+\_\+\+State\+Type\+Def}} \{ \newline
\mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4adbc218df2c9841b561282b40b3ded69d}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+RESET}} = 0x00\+UL
, \mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4abb3992c67a15c14bd1808ef6b63fa926}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+READY}} = 0x01\+UL
, \mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4a0635e168bc0430253fe8e74cfe9768fd}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+BUSY}} = 0x02\+UL
, \mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4a5d82b644c7ca656ab5fe8a8e3cbc29ab}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+TX}} = 0x03\+UL
, \newline
\mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4afd7e00128aca1feaa099c2595ffb9277}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+RX}} = 0x04\+UL
, \mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4a9dae2883ae3e43ca28afc9453a14c938}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+BUSY\+\_\+\+TX\+\_\+\+RX}} = 0x05\+UL
, \mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4a3cba266d2346abe3b62fa0acccab4711}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+ERROR}} = 0x06\+UL
, \mbox{\hyperlink{group___s_p_i___exported___types_gga8891cb64e76198a860172d94c638c9b4a34f9231d040d752a034db85e3eb7f782}{HAL\+\_\+\+SPI\+\_\+\+STATE\+\_\+\+ABORT}} = 0x07\+UL
 \}
\begin{DoxyCompactList}\small\item\em HAL SPI State structure definition. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Init} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+De\+Init} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void \mbox{\hyperlink{group___s_p_i___exported___functions___group1_ga17f583be14b22caffa6c4e56dcd035ef}{HAL\+\_\+\+SPI\+\_\+\+Msp\+Init}} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void \mbox{\hyperlink{group___s_p_i___exported___functions___group1_gabadc4d4974af1afd943e8d13589068e1}{HAL\+\_\+\+SPI\+\_\+\+Msp\+De\+Init}} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Transmit} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, const uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Receive} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Transmit\+Receive} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, const uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Tx\+Data, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Rx\+Data, uint16\+\_\+t Size, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Transmit\+\_\+\+IT} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, const uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Receive\+\_\+\+IT} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Transmit\+Receive\+\_\+\+IT} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, const uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Tx\+Data, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Rx\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Transmit\+\_\+\+DMA} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, const uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Receive\+\_\+\+DMA} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Transmit\+Receive\+\_\+\+DMA} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi, const uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Tx\+Data, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Rx\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+DMAPause} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+DMAResume} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+DMAStop} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Abort} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Abort\+\_\+\+IT} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+IRQHandler} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+Tx\+Cplt\+Callback} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void \mbox{\hyperlink{group___s_p_i___exported___functions___group2_ga3df7021fe24cf874f8b1eec5bd5f4cb3}{HAL\+\_\+\+SPI\+\_\+\+Rx\+Cplt\+Callback}} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\begin{DoxyCompactList}\small\item\em 当\+SPI接收完成,将会调用此回调函数,可以进行协议解析或其他必须的数据处理等 \end{DoxyCompactList}\item 
void \mbox{\hyperlink{group___s_p_i___exported___functions___group2_ga04e63f382f172164c8e7cae4ff5d883c}{HAL\+\_\+\+SPI\+\_\+\+Tx\+Rx\+Cplt\+Callback}} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\begin{DoxyCompactList}\small\item\em 和\+Rx\+Cplt\+Callback共用解析即可,这里只是形式上封装一下,不用重复写 这是对\+HAL库的\+\_\+\+\_\+weak函数的重写,传输使用\+IT或\+DMA模式,在传输完成时会调用此函数 \end{DoxyCompactList}\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+Tx\+Half\+Cplt\+Callback} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+Rx\+Half\+Cplt\+Callback} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+Tx\+Rx\+Half\+Cplt\+Callback} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+Error\+Callback} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+Abort\+Cplt\+Callback} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
void {\bfseries HAL\+\_\+\+SPI\+\_\+\+Suspend\+Callback} (\mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
\mbox{\hyperlink{group___s_p_i___exported___types_ga8891cb64e76198a860172d94c638c9b4}{HAL\+\_\+\+SPI\+\_\+\+State\+Type\+Def}} {\bfseries HAL\+\_\+\+SPI\+\_\+\+Get\+State} (const \mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\item 
uint32\+\_\+t {\bfseries HAL\+\_\+\+SPI\+\_\+\+Get\+Error} (const \mbox{\hyperlink{group___s_p_i___exported___types_gab633e49dd034de2f3a1fe79853d78d18}{SPI\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}hspi)
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Header file of SPI HAL module. 

\begin{DoxyAuthor}{Author}
MCD Application Team 
\end{DoxyAuthor}
\begin{DoxyAttention}{Attention}

\end{DoxyAttention}
Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-\/\+IS. 